1. Field of the Invention
The present invention relates to a method of manufacturing thin film transistors in a liquid crystal display apparatus, and more particularly to a method of manufacturing thin film transistors arranged in a matrix form for driving a liquid crystal display panel used for image display such as a lap-top personal computer and a wall mounting television.
2. Description of the Related Art
It is being recognized that a display quality of a liquid crystal display panel in which thin film transistors (TFTs) are arranged in a matrix form has been improved to an extent matching that of a cathode-ray tube (CRT). However, the fact is that the yield in a manufacturing process is low due to disconnection and short-circuit of interconnection or lack of uniformity in transistor characteristic of TFTS, etc., and this problem has to be eliminated.
In general, when a plurality of TFTs connected in a matrix form are formed on a substrate, a patterning process using 7 to 8 sheets of masks is required in a process which may be materialized as industrial production.
At present, the process for forming TFTs for liquid crystal drive using a-Si in a matrix form is roughly divided into an amorphous silicon etching stopper type using a channel protective film and an channel etching type using no channel protective film. As a citation related to a structure of an etching stopper type TFT, F. Funada et al., SID 1986 DIGEST pp. 293-295 for instance is available, and as a Patent Publication related to a channel etching type TFT, Japanese Unexamined Publication No. 293567/1989 for instance is available.
FIGS. 1A,1B to FIGS. 5A,5B are explanatory views of a principal part of an etching stopper type TFT in a matrix form at an important position of a process for explaining prior art. In these figures, FIG. 1A to FIG. 5A on the left sides show plan views of a principal part, and FIG. 1B to FIG. 5B on the right sides show sectional views taken along the line X--X, respectively. Here, in the plan views of a principal part, a part of formed layers is omitted in illustrations for the sake of simplicity.
The manufacturing process will be described hereinafter with reference to these figures, but the object here is TFTs arranged in a matrix form (hereinafter referred to as a TFT matrix) with reverse stagger type insulated gate TFTs using a-Si as a semiconductor active layer as switching elements.
First, the process until states shown in FIG. 1A and FIG. 1B are produced.
In the first place, a Ti film is formed on a substrate 1 composed of a transparent insulator such as glass. Then, a photoresist process and an reactive ion etching (RIE) in lithography technique are applied, and patterning is applied to the Ti film so as to form a gate electrode 2 and a gate bus line (a scanning bus line) 3 as shown in FIG. 1A.
Furthermore, as shown in FIG. 1B, a gate insulator film 4 composed of silicon nitride (SIN), an active layer 5 composed of a-Si and a channel protective film 6 composed of silicon nitride (SIN) are formed.
Next, patterning is applied to the channel protective film 6 by applying a photoresist process and a wet etching method as lithography techniques, thereby to leave the channel protective film 6 having a width narrower than that of the gate electrode 2 on the gate electrode 2 only as shown in FIG. 2A and FIG. 2B.
Thereafter, an electrode contact layer 7 composed of n.sup.+ -a-Si is formed on the whole surface. Then, patterning is applied to the electrode contact layer 7 and the active layer 5 by applying a photoresist process and an RIE. With this, the electrode contact layer 7 and the active layer 5 are formed into an island shape as shown in FIG. 3A and FIG. 3B.
Thereafter, a Ti film is formed on the whole surface. Then, a photoresist mask and a plasma etching method are applied as lithography techniques thereby to apply patterning to the Ti film, and a source electrode 8, a drain electrode 9 and a drain bus line (a data bus line) 10 are formed as shown in FIG. 4A and FIG. 4B. Next, patterning is applied to the electrode contact layer 7 by using the photoresist mask, and a gas containing CF.sub.4 and O.sub.2.
Next, a photoresist process and a plasma etching method is applied as lithography techniques, and the gate insulator film 4 covering a gate bus terminal portion 3A shown in FIG. 6 located at the end of the gate bus line 3 is etched selectively thereby to form an opening.
Thereafter, an indium tin oxide (ITO) film is formed on the whole surface. Furthermore, patterning is applied to the ITO film by applying a photoresist process and a wet etching method as lithography techniques, thereby to form a pixel electrode 11 shown in FIG. 5A and FIG. 5B and a gate bus terminal 12 shown in FIG. 6. And, the ITO film is remained on drain bus terminals(not shown).
Thereafter, it is required to form a final protective film not shown and to apply patterning thereto by lithography techniques to remove the final protective film on the bus terminals and the pixel electrode 11.
The masks of photoresist up to this point is 7 in number.
When it is demanded to reduce the resistance of the bus line in the process described above, patterning is applied only to the bus line separately as described later, and the patterning process is thereby increased further.
Here, it will be described how to make the bus line low in resistance.
In general, the resistance value required for the bus line is 20 K.OMEGA. or lower for the gate bus line and 35 K.OMEGA. or lower for the drain bus line in a VGA mode color panel (gate: 480 lines, drain: 640.times.3 lines) of approximately 26 cm (10.4 inch) for instance.
Such requirement is loose for a small-sized device such as for a pocket type television and a projection type television, and it is strict for a large-sized device such as for a work station and HDTV.
In the case of a down gate stagger type TFT structure aimed at by the present invention, requirement for low resistance is more strict in the gate bus line. However, such problems are caused that 1 the gate bus line can not be made thicker because it forms a lower layer of the gate insulator film, 2 when aluminum which is a material of a low resistance is used in the upper side of the gate bus line, hillock, whisker or the like is generated on the gate bus line by forming an insulator film by a high temperature process thereafter, 3 when the gate electrode material is made thicker, it becomes necessary to use a special technique such as taper etching and so on.
As a means for evading such problems, after a gate bus line is formed with aluminum as the lowest layer, a gate bus line and a gate electrode composed of refractory metal such as Ti and Cr is formed so as to completely cover the gate bus line composed of aluminum in some cases. This corresponds to patterning only bus line described previously.
In the case of the down gate stagger type TFT, the drain bus line is formed on the gate insulator film and the required resistance value of the drain bus line is not so strict as that of the gate bus line. Then, the drain bus line is made of a thicker single film. However a multilayer is formed sometimes due to the requirement in the process or in order to obtain a redundant structure for disconnection. In this case, special patterning is required naturally.
In the prior art described with reference to FIG. 1A, FIG. 1B to FIG. 5A, FIG. 5B and FIG. 6, a patterning process using 7 or 8 photomasks becomes necessary, which exerts a big influence upon production yield. Hence, it is preferred that the process is less in the number of photomasks even by one.
Thus, such plans have been elaborated that 1 no channel protective film is used, 2 formation of an a-Si layer into an island shape and patterning of a source electrode, a drain electrode and a drain bus line are performed at the same time, 3 patterning is omitted by means of mask depositioning for exposing a gate terminal portion and forming the final protective film.
In any of the items 1 to 3 described above, some problems happen as described hereunder.
In the case of 1, the TFT has a channel etching type. According to this TFT, there are such advantages that plasma chemical vapor deposition processes are reduced due to a fact that non-doped a-Si which is a channel layer and n.sup.+ -a-Si which is a contact portion are formed successively, and that the patterning processes are reduced by one process since it is not required to form the channel protective film in an island shape.
However, it becomes necessary to remove n.sup.+ -a-Si only selectively among the multi-layer of a-Si and n.sup.+ -a-Si. Since both cannot be etched selectively, a-Si has to be formed thick in advance, and when a-Si is thick, such a problem that a cleaning cycle of a film forming apparatus becomes short thus lowering an operation rate or an off-current of the TFT is increased by photoelectrical effect is caused.
Further, as to the item 2, after patterning the deposition film of a-Si, n.sup.+ -a-Si and metal for the drain bus line it is required to cover the source electrodes by an ITO film which forms pixel electrodes so as to connect these electrodes electrically. However, unless the deposition film such as a-Si is patterned in a forward taper shape, the possibility of disconnection of the ITO film becomes very high by the edge of the deposition film. In particular, there is a problem that, when the film thickness is increased in order to make the drain bus line low in resistance, disconnection due to step difference is produced more easily.
Furthermore, as to the item 3, since the final protective film is formed for the purpose of damp proofing of the TFT, it is not necessarily required to form an opening in every pixel. It is at a terminal portion that removal is indispensable, but, since the pattern at that portion is comparatively coarse, a means of forming no film at the terminal portion only by inserting a metal mask on a substrate (mask deposition) can be adopted when the final protective film is formed.
However, as a matter of course, the film forming process becomes complicated, and the final protective film passes in between the terminal portion and the metal mask, thus producing a problem of poor contact of the terminal.